Conventionally, an analog-digital converter (hereinafter, referred to as “AD converter”) using a delta sigma (hereinafter, referred to as “ΔΣ”) modulator has been widely used (for example, see Non-Patent Document 1 (J. Silva, U. Moon, J. Steensgaard and G. Temes, “Wideband Low-distortion delta sigma ADC topology”, Electronics Letters, 7 Jun. 2001, Vo. 37, No. 12) and Non-Patent Document 2 (J. Silva, U. Moon, and G. Temes, “Low-distortion delta sigma topologies for MASH architectures, “IEEE Int. Symp. Circuits Syst., vol. I, pp. 1144-1147, May 2004)). Such a ΔΣ AD converter provides an input signal to an AD conversion section, and performs DA conversion of an output from the AD conversion section, and integrates a difference obtained by subtracting the DA-converted signal from the input signal, and provides the integrated signal to the AD conversion section. This ΔΣ AD converter makes it easier to realize highly accurate, low distortion, and low voltage operation. Thus, the ΔΣ AD converter is applied not only to an audio but also to a radio communication receiver or the like. Further, its over sampling rate is high, so that less performance is required in an Anti-Alias filter which is necessary at a preceding stage of the ΔΣ AD converter.
FIG. 13 is a block diagram schematically illustrating a conventional ΔΣ AD converter 90. The ΔΣ AD converter 90 includes a buffer circuit 91 for supplying an input signal X to a switched-capacitor sampling section 92 and an adder 97. The sampling section 92 samples the input signal X supplied from the buffer circuit 91 and outputs the sampled signal X to a subtracter 93.
The adder 97 adds an output signal Y1 of a loop filter 96 to the input signal X supplied from the buffer circuit 91 and outputs the resultant to an AD conversion section 95. The AD conversion section 95 converts the output of the adder 97 into a signal having an N-bit digital value and outputs the converted signal as an output voltage V and provides the converted signal to a DA conversion section 94. The DA conversion section 94 converts the output of the AD conversion section 95 into a signal having an analog value and provides the signal to the subtracter 93. The subtracter 93 subtracts the output of the DA conversion section 94 from the output of the sampling section 92 and provides the resultant to the loop filter 96. The loop filter 96 outputs the output signal Y1 obtained by integrating the output of the subtracter 93 to the adder 97.
FIG. 14 is a detail block diagram illustrating a linear model in which the order of the loop filter 96 of the ΔΣ AD converter 90 is the first order. In FIG. 14, the AD converter 95 (FIG. 13) is modeled as an adder 98, and a sum of a quantization noise E(z) and the output signal supplied from the adder 97 to the AD conversion section 95 (FIG. 13) is an output signal of the AD conversion section 95 (FIG. 13). In this case, the following Expressions 1 and 2 hold.V(z)=X(z)+(1−z−1)·E(z)  Expression 1Y0(z)=X(z)−V(z)=−(1−z−1)·E(z)  Expression 2
According to the Expressions 1 and 2, the input signal X(z) is not inputted to the loop filter 96 and the loop filter 96 deals with only the shaped quantization noise E(z). Thus, any distortion of the input signal X(z) caused by the nonlinearity of the active component in the loop filter 96 does not occur. Thus, it is possible to realize a ΔΣ AD converter causing less distortion.
Further, there is widely used a pipelined AD converter arranged so that: an input signal is provided to an AD conversion section, and a signal obtained by performing DA conversion with respect to an output of the AD conversion section is subtracted from the input signal and the resultant is amplified, and the amplified signal is provided to a following pipeline stage (for example, see Non-Patent Document 3 (E. Siragusa, “A digitally Enhanced 1.8-V15-bit 40-MS/s CMOS Pipelined ADC”, IEEE Journal of Solid-State Circuits, Vol. 39, No. 12, December 2004 pp. 2132)).
Further, a switched-capacitor amplifier is widely used for various purposes of use (for example, see Patent Document 1 (Japanese Unexamined Patent Application No. 243949/2003 (Tokukai 2003-243949)(Publication date: Aug. 29, 2003)), FIG. 5).
However, in the conventional ΔΣ AD converter 90, the input signal X(z) is not inputted to the loop filter 96. Thus, it is necessary to cause the subtracter 93 to offset (i) an input signal X component which passes through a signal path 81 and a signal path 82 and is converted into a signal having a digital value by the AD conversion section 95, and passes through a signal path 83 and is converted into a signal having an analog value by the DA conversion section 94 and (ii) an input signal X component which is sampled so as to be outputted by the sampling section 92. Therefore, it is necessary that the input signal X component passes through the signal path 81, the signal path 82, and the signal path 83 without delay to reach the subtracter 93. Thus, the signal path 81, the signal path 82, and the signal path 83 have to be free from any delay, so that it is necessary to so sufficiently reduce a delay quantity of the AD conversion section 95 and a delay quantity of the DA conversion section 94 that the delay quantities do not raise any problem compared with an operation frequency of the ΔΣ AD converter 90.
Further, the output of the DA conversion section 94 is a multi-valued output, so that distortion caused by unevenness of elements constituting the DA conversion section occurs. In order to reduce the distortion, mismatch shaping is often adopted. A digital circuit realizing the mismatch shaping is disposed above the signal path 83, so that it is necessary to reduce a delay quantity of the mismatch shaping digital circuit too.
In case of reducing the delay quantity of the AD conversion section 95, the delay quantity of the DA conversion section 94, and the delay quantity of the mismatch shaping digital circuit, circuit sizes and power consumption of the DA conversion section 94 and the mismatch shaping digital circuit increase. This is a problem of the conventional ΔΣ AD converter 90.
Also in the pipelined AD converter, it is necessary to so sufficiently reduce the delay quantity of the AD conversion section and the delay quantity of the DA conversion section compared with an operation frequency of the whole converter. Thus, the AD conversion section and the DA conversion section have to finish a signal process in sufficiently short time compared with the operation frequency of the whole converter (see Non-Patent Document 3, FIG. 11). As a result, it is necessary to reduce the delay quantities of the AD conversion section, the DA conversion section, and the like, so that circuit sizes and power consumption increase. This is a problem of the conventional pipelined AD converter.